1. Field of the Invention
The present invention relates to large scale integrated circuits and more particularly to an integrated circuit using a serial scan test with reduced power dissipation.
2. Prior Art
A method used for testing integrated circuits is the scan-path built-in test structure approach. There are many variations to this approach including multiplexed scan, clocked scan, and level sensitive scan design. When incorporating scan-path capability into an integrated circuit (IC), standard register devices are replaced with modified test registers which have a test mode of operation. FIG. 1 shows such a test register 10 for a scan-path structure. The test register 10 has a test data input TDI for receiving test data input signals 11, in addition to the regular functional data input D, for receiving functional data signals 12. Conventional scan enable SE and clock inputs, for receiving scan enable signals 13 and clock signals 14, and a data output Q for output signals 15, are also provided. A series of such test registers are connected together to form a serial shift register or registers allowing test data to be loaded into all the registers in a memory or other device to set up conditions for testing. FIG. 2 shows on exemplary circuit incorporating scan-path testing. After loading test data into the test registers of a device the same scan-path path can be used to observe the result by serial shifting out the state of the registers. Controllability and observability of internal circuit nodes is achieved in this manner and is used for the purposes of fault detection. The integrated circuit may be partitioned for testing purposes into one or more serial shift register chains.
As seen in FIG. 2 conventional scan-path circuits are implemented by connecting the output signal 15 from one register 30 to the test data input TDI of another register 32. In addition to this connection, needed for scan-path capability, the output signal 15 of one register (30) is also coupled to the functional data input D of another register (32) through combinatorial logic or registers 34 to achieve the logic and control functions desired.
A source of power dissipation in an integrated circuit is the charging and discharging of capacitances which occurs when logic signals go through transitions from a high to a low voltage state or a low to a high voltage state. The circuit interconnections between gates and the MOS transistors forming gates both have capacitance that is charged and discharged when logic signals transition. When scan-path signal paths are added to an IC, there is an increase in the capacitance being driven due to the increase in the length of the interconnection and the additional gate load at the test data input of the test register. Thus, an increase in total power dissipation is experienced when scan-path capability is incorporated into an IC. In a large scale integrated circuit there are many such paths that contribute to increased power dissipation.
Further background on scan-path testing is described in Chapter 6 of Submicron ASIC Products Design for Testability Reference Guide 1993, published by Texas Instruments.
Objects
An object of the present invention is to provide an integrated circuit device with a scan-path test structure having reduced power dissipation.